/* ------------------------------------------------------------------------------------------------ */
/* FILE :		uAbassiCfgA53.c																		*/
/*																									*/
/* CONTENTS :																						*/
/*				Configuration file for uAbassi for uAbassi											*/
/*																									*/
/*																									*/
/* Copyright (c) 2014-2019, Code-Time Technologies Inc. All rights reserved.						*/
/*																									*/
/* Code-Time Technologies retains all right, title, and interest in and to this work				*/
/*																									*/
/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS							*/
/* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF										*/
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL							*/
/* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR								*/
/* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,							*/
/* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR							*/
/* OTHER DEALINGS IN THE SOFTWARE.																	*/
/*																									*/
/*																									*/
/*	$Revision: 1.2 $																				*/
/*	$Date: 2019/01/10 18:07:13 $																	*/
/*																									*/
/* ------------------------------------------------------------------------------------------------ */
/*																									*/
/* Contains the following configuration for uAbassi													*/
/*																									*/
/*	Type of multi-processing:																		*/
/*		G_OS_MP_TYPE     = 2U true SMP																*/
/*		                 = 3U packed SMP															*/
/*		                 = 4U true BMP																*/
/*		                 = 5U packed BMP															*/
/*																									*/
/*		G_OS_START_STACK = Stack size (bytes) of the Idle Core tasks (when no task run on a core)	*/
/*																									*/
/*		G_OS_TIMER_US    = Timer tick in us (only used for sec <--> tick conversion macros			*/
/*																									*/
/*  MMU / Cache defintion tables																	*/
/*																									*/
/* ------------------------------------------------------------------------------------------------ */

#include "uAbassi.h"

#ifndef OS_MP_TYPE
  #define OS_MP_TYPE		4U						/* If not def in build, set desired value here	*/
#endif
#ifndef OS_START_STACK
  #define OS_START_STACK	32768					/* If not def in build, set desired value here	*/
#endif

/* ------------------------------------------------------------------------------------------------ */

const unsigned int G_OS_MP_TYPE   = OS_MP_TYPE;		/* Type of multi-processing. See documentation	*/
const int        G_OS_START_STACK = OS_START_STACK;	/* Stack size in bytes of each CoreIdle tasks	*/
const int        G_OS_TIMER_US    = OS_TIMER_US;	/* Application specific value					*/


													/* MMU table definitions. See documentation		*/
#if (((OS_PLATFORM) & 0x00FFFFFF) == 0x00007753)	/* UltraScale+ memory map						*/
/*                                          LENGTH               BASE ADDR							*/
  const int64_t G_MMUsharedTbl[]    = { 
                    0x0080000000LL, 0x0000000000LL,	/* 0x00_0000_0000 -> 0x00_7FFF_FFFF - DDR		*/
                    0x00000C0000LL, 0x00FFE00000LL,	/* 0x00_FFE0_0000 -> 0x00_FFFB_FFFF - TCM		*/
                    0x0800000000LL, 0x0800000000LL,	/* 0x08_0000_0000 -> 0x0F_FFFF_FFFF - DDR		*/
                    0x0000000000LL    };			/* End of the table								*/

  const int64_t G_MMUnonCachedTbl[] = {
                    0x0040000000LL, 0x0080000000LL,	/* 00_8000_0000 -> 00_BFFF_FFFF - PL			*/
                    0x0030000000LL, 0x00C0000000LL,	/* 00_C000_0000 -> 00_EFFF_FFFF - QSPI,lowPCIe	*/
                    0x0001000000LL, 0x00F8000000LL,	/* 00_F800_0000 -> 00_F8FF_FFFF - STMcoresight	*/
                    0x0000200000LL, 0x00F9000000LL, /* 00_F900_0000 -> 00_F91F_FFFF - GIC			*/
                    0x0002C00000LL, 0x00FD000000LL,	/* 00_FD00_0000 -> 00_FFBF_FFFF - FPS,LPS slv	*/
                    0x0000200000LL, 0x00FFC00000LL,	/* 00_FFC0_0000 -> 00_FFDF_FFFF - CSU, PMU		*/
                    0x0000040000LL, 0x00FFFC0000LL,	/* 00_FFFC_0000 -> 00_FFFF_FFFF - OCM			*/
                    0x0400000000LL, 0x0400000000LL,	/* 04_0000_0000 -> 07_FFFF_FFFF - PL, PCIe		*/
                    0xB000000000LL, 0x1000000000LL,	/* 10_0000_0000 -> CF_FFFF_FFFF - PL, PCIe		*/
                    0x0000000000LL    };			/* End of the table								*/

  const int64_t G_MMUprivateTbl[] =   { 
                    0x0000000000LL,					/* Nothing for core #0							*/
                    0x0000000000LL,					/* Nothing for core #1							*/
                    0x0000000000LL,					/* Nothing for core #2							*/
                    0x0000000000LL    };			/* Nothing for core #3							*/


  const int64_t G_MMUnonCprivTbl[] =  {
                    0x0000000000LL,					/* Nothing for core #0							*/
                    0x0000000000LL,					/* Nothing for core #1							*/
                    0x0000000000LL,					/* Nothing for core #2							*/
                    0x0000000000LL    };			/* Nothing for core #3							*/
#endif

/* EOF */
